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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD7801 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1997 +2.7 v to +5.5 v, parallel input, voltage output 8-bit dac functional block diagram input register dac register i dac ? 2 power-on reset AD7801 v out agnd pd clr ldac refin v dd dgnd d7 d0 wr cs i/v mux control logic features single 8-bit dac 20-pin soic/tssop package +2.7 v to +5.5 v operation internal and external reference capability dac power-down function parallel interface on-chip output buffer rail-to-rail operation low power operation 1.75 ma max @ 3.3 v power-down to 1 m a max @ 25 8 c applications portable battery powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators general description the AD7801 is a single, 8-bit, voltage out dac that operates from a single +2.7 v to +5.5 v supply. its on-chip precision output buffer allows the dac output to swing rail to rail. the AD7801 has a parallel microprocessor and dsp compatible interface with high speed registers and double buffered interface logic. data is loaded to the input register on the rising edge of cs or wr . reference selection for the AD7801 can be either an internal reference derived from the v dd or an external reference applied at the refin pin. the output of the dac can be cleared by using the asynchronous clr input. the low power consumption of this part makes it ideally suited to portable battery operated equipment. the power consump- tion is less than 5 mw at 3.3 v, reducing to less than 3 m w in power-down mode. the AD7801 is available in a 20-lead soic and a 20-lead tssop package. product highlights 1. low power, single supply operation. this part operates from a single +2.7 v to +5.5 v supply and consumes typically 5 mw at 3 v, making it ideal for battery powered applications. 2. the on-chip output buffer amplifier allows the output of the dac to swing rail to rail with a settling time of typically 1.2 m s. 3. internal or external reference capability. 4. high speed parallel interface. 5. power-down capability. when powered down the dac consumes less than 1 m a at 25 c. 6. packaged in 20-lead soic and tssop packages.
C2C rev. 0 AD7801Cspecifications (v dd = +2.7 v to +5.5 v, internal reference; c l = 100 pf, r l = 10 k v to v dd and gnd. all specifications t min to t max unless otherwise noted.) parameter b versions 1 units conditions/comments static performance resolution 8 bits relative accuracy 2 1 lsb max differential nonlinearity 1 lsb max guaranteed monotonic zero-code error @ +25 c 3 lsb typ all zeros loaded to dac register full-scale error C0.75 lsb typ all ones loaded to dac register zero-code error drift 100 m v/ c typ gain error 3 1 % fsr typ dac reference input refin input range 1 to v dd /2 v min/v max refin input impedance 10 m w typ output characteristics output voltage range 0 to v dd v min/v max output voltage settling time 2 m s max typically 1.2 m s slew rate 7.5 v/ m s typ digital-to-analog glitch impulse 1 nv-s typ 1 lsb change around major carry digital feedthrough 0.2 nv-s typ dc output impedance 40 w typ short circuit current 14 ma typ power supply rejection ratio 4 0.0003 %/% max d v dd = 10% logic inputs input current 10 m a max v inl , input low voltage 0.8 v max v dd = +5 v v inl , input low voltage 0.6 v max v dd = +3 v v inh , input high voltage 2.4 v min v dd = +5 v v inh , input high voltage 2.1 v min v dd = +3 v pin capacitance 7 pf max power requirements v dd 2.7/5.5 v min/v max i dd (normal mode) dac active and excluding load current v dd = 3.3 v v ih = v dd and v il = gnd @ 25 c 1.55 ma max see figure 6 t min to t max 1.75 ma max v dd = 5.5 v @ 25 c 2.35 ma max t min to t max 2.5 ma max i dd (power-down) @ 25 c1 m a max v ih = v dd and v il = gnd t min to t max 2 m a max see figure 18 notes 1 temperature ranges are as follows: b version: C40 c to +105 c 2 relative accuracy is calculated using a reduced code range of 15 to 245. 3 gain error is specified between codes 15 and 245. the actual error at code 15 is typically 3 lsb. 4 guaranteed by characterization at product release, not production tested. specifications subject to change without notice. figure 1. timing diagram for parallel data write t 1 t 2 t 4 t 3 t 5 t 6 t 7 t 8 cs wr d7-d0 ldac clr
AD7801 C3C rev. 0 timing characteristics 1, 2 limit at t min , t max parameter (b version) units conditions/comments t 1 0 ns min chip select to write setup time t 2 0 ns min chip select to write hold time t 3 20 ns min write pulse width t 4 15 ns min data setup time t 5 4.5 ns min data hold time t 6 20 ns min write to ldac setup time t 7 20 ns min ldac pulse width t 8 20 ns min clr pulse width notes 1 sample tested at +25 c to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. tr and tf should not exceed 1 m s on any digital input. 2 see figure 1. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD7801 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings* (t a = +25 c unless otherwise noted) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v reference input voltage to agnd . . . . C0.3 v to v dd + 0.3 v digital input voltage to dgnd . . . . . . C0.3 v to v dd + 0.3 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . . C0.3 v to +0.3 v v out to agnd . . . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v operating temperature range commercial (b version) . . . . . . . . . . . . . C40 c to +105 c storage temperature range . . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150 c ssop package, power dissipation . . . . . . . . . . . . . . . 700 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . 143 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220 c soic package, power dissipation . . . . . . . . . . . . . . . 870 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 74 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide temperature package model range option* AD7801br C40 c to +105 c r-20 AD7801bru C40 c to +105 c ru-20 *r = small outline; ru = thin shrink small outline. (v dd = +2.7 v to +5.5 v; gnd = 0 v; internal v dd /2 reference. all specifications t min to t max unless otherwise noted.)
AD7801 C4C rev. 0 pin function descriptions pin no. mnemonic function 1C8 d7Cd0 parallel data inputs. 8-bit d ata is loaded to the input register of the AD7801 under the control of cs and wr . 9 cs chip select. active low logic input. 10 wr write input. wr is an active low logic input used in conjunction with cs to write data to the input register. 11 dgnd digital ground 12 pd active low input used to put the part into low power mode reducing current consumption to less than 1 m a. 13 ldac load dac logic input. when this logic input is taken low the dac output is updated with the contents of its dac register. if ldac is permanently tied low the dac is updated on the rising edge of wr . 14 clr asynchronous clear input (active low). when this input is taken low the dac register is loaded with all zeroes and the dac output is cleared to zero volts. 15 v dd power supply input. this part can be operated from +2.7 v to +5.5 v and should be decoupled to gnd. 16 refin external reference input. this can be used as the reference for the dac. the range on this refer ence input is 1 v to v dd /2. if refin is tied directly to v dd the internal v dd /2 reference is selected. 17 agnd analog ground reference point and return point for all analog current on the part. 18 nc no connect pin. 19 v out analog output voltage from the dac. the output amplifier can swing rail to rail on its output. 20 dgnd digital ground reference point and return point for all digital current on the part. pin configuration 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) AD7801 nc = no connect (msb) db7 agnd nc v out dgnd db6 db5 db4 clr v dd refin db3 db2 db1 (lsb) db0 cs wr dgnd pd ldac
AD7801 C5C rev. 0 sink current ?ma v out ?mv 800 0 08 24 6 720 400 240 160 80 640 560 320 480 v dd = 5v and 3v internal reference t a = +25 c dac loaded with 00hex figure 2. output sink current capa- bility with v dd = 3 v and v dd = 5 v reference voltage ?volts error ?lsbs 0.5 0 1.0 1.2 2.8 1.4 1.6 1.8 2.2 2.4 2.6 2.0 0.45 0.25 0.15 0.1 0.05 0.4 0.35 0.2 0.3 v dd = 5v t a = +25 c inl error dnl error figure 5. relative accuracy vs. external reference frequency ?hz attenuation ?db 1 10 10k 100 1k 10 5 ?0 0 ? ?0 ?5 ?0 ?5 ?0 ?5 v dd = 5v external sinewave reference dac register loaded with ffhex t a = +25 c figure 8. large scale signal frequency response typical performance characteristicsC source current ?ma v out volts 02 8 46 5 4.92 4.2 4.84 4.76 4.68 4.6 4.52 4.44 4.36 4.28 v dd = 5v internal reference dac register loaded with ffhex t a = +25 c figure 3. output source current capability with v dd = 5 v ?0 ?5 100 temperature ? c 3.5 2.0 i dd ?ma 4.0 3.0 2.5 internal reference logic inputs = v dd or gnd dac active v dd = 5.5v v dd = 3.3v 1.5 1.0 0.5 0 0 255075 125 figure 6. typical supply current vs. temperature t ? v out v dd = 3v internal voltage reference full scale code change 00h-ffh t a = +25 c 1 ? 3 ? 2 ? v out ch1 5v, ch2 1v, ch3 20mv time base = 200 ns/div wr figure 9. full-scale settling time source current ?ma 3.5 1.0 01 8 234567 3.25 2.5 2.25 1.75 1.25 3.0 2.75 2.0 1.5 v out ?volts v dd = 3v internal reference dac register loaded with ffhex t a = +25 c figure 4. output source current capability with v dd = 3 v v dd ?volts i dd ?ma 3.0 1.0 4.0 2.5 3.0 5.5 3.5 4.0 4.5 5.0 logic inputs = v dd or gnd logic inputs = v ih or v il dac active internal reference t a = +25 c 2.0 0 figure 7. typical supply current vs. supply voltage pd v out AD7801 power-up time v dd = 5v internal reference dac in power-down initially 1 ? 2 ? ch1 = 2v/div, ch2 = 5v/div, time base = 2 m s/div figure 10. exiting power-down (full power-down)
AD7801 C6C rev. 0 1 2 m20.0ms v out v dd ch1 5.00v ch2 5.00v ch1 t t figure 11. power-onreset input code (15 to 245) inl error ?lsb 0 256 32 64 96 128 160 192 224 ?.5 0.4 0.1 ?.1 ?.3 ?.4 0.3 0.2 0 ?.2 0.5 v dd = 5v internal reference 5k w 100pf load limited code range (15?45) t a = +25 c figure 14. integral linearity plot Ctypical performance characteristics ?5 4 0 7 6 2 1 5 3 8 9 10 ?0 0 25 50 75 100 125 temperature ? c zero code error ?lsb vdd = 2.7 to 5.5v dac loaded with all zeroes internal reference figure 12. zero code error vs. temperature v dd = 5v internal reference 0.5 0.4 0.3 0.2 0.1 0 ?.1 ?.2 ?.3 ?.4 ?.5 ?0 ?0 ?0 0 20 40 60 80 100 120 140 inl error ?lsb temperature ? c figure 15. typical inl vs. temperature 2 ? 1 ? wr v out v dd = 5v internal voltage reference 10 lsb step change t a = +25 8 c ch1 5.00v, ch2 50.0mv, m 250ns figure 13. small-scale settling time v dd = 5v internal reference 0.5 0.4 0.3 0.2 0.1 0 ?.1 ?.2 ?.3 ?.4 ?.5 ?0 ?0 ?0 0 20 40 60 80 100 120 140 temperature ? c dnl error ?lsb figure 16. typical dnl vs. temperature v dd = 5v 0.6 0.4 0.2 0 ?0 ?0 ?0 0 20 40 60 80 100 120 140 temperature ? c int reference error ? % 0.8 1.0 figure 17. typical internal reference error vs. temperature temperature ? c 0 ?0 ?5 150 v dd = 5v logic inputs = v dd or gnd 100 200 300 400 500 600 700 800 900 1000 power down current ?na 0 255075100 figure 18. power-down current vs. temperature
AD7801 C7C rev. 0 terminology integral nonlinearity for the dac, relative accuracy or end-point nonlinearity is a measure of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. a graphical representation of the transfer curve is shown in figure 14. differential nonlinearity differential nonlinearity is the difference between the mea- sured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. zero-code error zero-code error is the measured output voltage from v out of the dac when zero code (all zeros) is loaded to the dac latch. it is due to a combination of the offset errors in the dac and output amplifier. zero-code error is expressed in lsbs. gain error this is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from ideal expressed as a percent of the full-scale value. it includes full- scale errors but not offset errors. digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the digital inputs change state with the dac selected and the ldac used to update the dac. it is normally specified as the area of the glitch in nv-secs and measured when the digital input code is changed by 1 lsb at the major carry transition. digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of a dac from the digital inputs of the same dac, but is measured when the dac is not updated. it is specified in nv-secs and measured with a full-scale code change on the data bus, i.e., from all 0s to all 1s and vice versa. power supply rejection ratio (psrr) this specification indicates how the output of the dac is affected by changes in the power supply voltage. power supply rejection ratio is quoted in terms of % change in output per % change in v dd for full-scale output of the dac. v dd is varied 10%. general description d/a section the AD7801 is an 8-bit voltage output digital-to-analog con- verter. the architecture consists of a reference amplifier and a current source dac followed by a current-to-voltage converter capable of generating rail-to-rail voltages on the output of the dac. figure 19 shows a block diagram of the basic dac architecture. AD7801 v out refin i/v 11.7k w 11.7k w current dac 30k w 30k w v dd reference amplifier figure 19. dac architecture the dac output is internally buffered and has rail-to-rail output characteristics. the output amplifier is capable of driving a load of 100 pf and 10 k w to both v dd and ground. the reference selection for the dac can be either internally gener- ated from v dd or externally applied through the refin pin. a comparator on the refin pin detects whether the required reference is the internally generated reference or the externally applied voltage to the refin pin. if refin is connected to v dd , the reference selected is the internally generated v dd /2 reference. when an externally applied voltage is more than one volt below v dd , the comparator selection switches to the externally applied v oltage on the refin pin. the range on the external reference input is from 1.0 v to v dd /2 v. the output voltage from the dac is given by: v o = 2 v ref n 256 ? ? ? ? where v ref is the voltage applied to the external refin pin or v dd /2 when the internal reference is selected. n is the decimal equivalent of the code loaded to the dac register and ranges from 0 to 255. vth pmos mux int ref comparator selected reference output v dd ref in int ref ext ref figure 20. reference selection circuitry
AD7801 C8C rev. 0 reference the AD7801 has the ability to use either an external reference applied through the refin pin or an internal reference generated from v dd . figure 20 shows the reference input arrangement where either the internal v dd /2 or the externally applied reference can be selected. the internal reference is selected by tying the refin pin to v dd . if an external reference is to be used, this can be directly applied to the refin pin and if this is 1 v below v dd , the internal circuitry will select this externally applied reference as the reference source for the dac. digital interface the AD7801 contains a fast parallel interface allowing this dac to interface to industry standard microprocessors, microcontrollers and dsp machines. there are two modes in which this parallel interface can be configured to update the dac output. the synchronous update mode allows synchro- nous updating of the dac output; the automatic update mode allows the dac to be updated individually following a write cycle. figure 21 shows the internal logic associated with the digital interface. the pon strb signal is internally generated from the power-on reset circuitry and is low during the power- on reset phase of the power up procedure. clear set sle ldac enable dac control logic mle sle clr pon strb clr ldac cs wr figure 21. logic interface the AD7801 has a double buffered interface, which allows for synchronous updating of the dac output. figure 22 shows a block diagram of the register arrangement within the AD7801. mle sle control logic cs wr ldac clr 4 15 15 30 8 input register 4 to 15 decoder dac register 4 15 15 30 4 to 15 decoder dac register drivers lower nibble upper nibble db7-db0 drivers figure 22. register arrangement automatic update mode in this mode of operation the ldac signal is permanently tied low. the state of the ldac is sampled on the rising edge of wr . ldac being low allows the dac register to be automati- cally updated on the rising edge of wr . the output update occurs on the rising edge of wr . figure 23 shows the timing associated with the automatic update mode of operation and also the status of the various registers during this frame. hold hold track track d7-d0 wr cs ldac = 0 i/p reg (mle) dac reg (sle) v out track hold figure 23. timing and register arrangement for auto- matic update mode synchronous update mode in this mode of operation the ldac signal is used to update the dac output to synchronize with other updates in the system. the state of the ldac is sampled on the rising edge of wr . if ldac is high, the automatic update mode is disabled and the dac latch is updated at any time after the write by taking ldac low. the output update occurs on the falling edge of ldac . ldac must be taken back high again before the next data transfer takes place. figure 24 shows the timing associated with the synchronous update mode of operation and also the status of the various registers during this frame. hold hold d7-d0 wr cs ldac i/p reg (mle) dac reg (sle) v out hold hold track track figure 24. timing and register arrangement for synchro- nous update mode
AD7801 C9C rev. 0 v o ut = 2 v ref n 256 ? ? ? ? where: n is the decimal equivalent of the binary input code. n ranges from 0 to 255. v ref is the voltage applied to the external refin pin when the external reference is selected and is v dd /2 if the internal reference is used. table i. output voltage for selected input codes digital analog output msb . . . lsb 1111 1111 2 255 256 v ref v 1111 1110 2 254 256 v ref v 1000 0001 2 129 256 v ref v 1000 0000 v ref v 0111 1111 2 127 256 v ref v 0000 0001 2 v ref 256 v 0000 0000 0 v 2v ref v ref 0 dac output voltage dac input code 00 01 7f 80 81 fe ff figure 26. dac transfer function power-on reset the AD7801 has a power-on reset circuit designed to allow output stability during power up. this circuit holds the dac in a reset state until a write takes place to the dac. in the reset state all zeros are latched into the input register of the dac and the dac register is in transparent mode thus the output of the dac is held at ground potential until a write takes place to the dac. the power-on reset circuitry generates a pon strb signal which is a gating signal used within the logic to identify a power-on condition. power-down features the AD7801 has a power-down feature implemented by exercising the external pd pin. an active low signal puts the complete dac into power-down mode. when in power-down, the current consumption of the device is reduced to less than 1 m a max at +25 c or 2 m a max over temperature, making the device suitable for use in portable battery powered equipment. the internal reference resistors, the reference bias servo loop, the output amplifier and associated linear circuitry are all shut down when the power-down is activated. the output terminal sees a load of ? 23 k w to gnd when in power-down mode as shown in figure 25. the contents of the data register are unaffected when in power-down mode. the device typically comes out of power-down in 13 m s (see figure 10). v dd 11.7k w 11.7k w i dac v ref figure 25. output stage during power-down analog outputs the AD7801 contains a voltage output dac with 8-bit resolution and rail-to-rail operation. the output buffer provides a gain of two at the output. figures 2, 3 and 4 show the source and sink capabilities of the output amplifier. the slew rate of the output amplifier is typically 7.5 v/ m s and has a full-scale settling to eight bits with a 100 pf capacitive load in typically 1.2 m s. the input coding to the dac is straight binary. table i shows the binary transfer function for the AD7801. figure 26 shows the dac transfer function for binary coding. any dac output voltage can be expressed as:
AD7801 C10C rev. 0 figure 27 shows a typical setup for the AD7801 when using its internal reference. the internal reference is selected by tying the refin pin to v dd . internally in the reference section there is a reference detect circuit that will select the internal v dd /2 based on the voltage connected to the refin pin. if refin is within a threshold voltage of a pmos device (approximately 1 v) of v dd the internal reference is selected. when the refin voltage is more than 1 v below v dd , the externally applied voltage at this pin is used as the reference for the dac. the internal reference on the AD7801 is v dd /2, the output current to voltage converter within the AD7801 provides a gain of two. thus the output range of the dac is from 0 v to v dd , based on table i. data bus control inputs AD7801 cs wr ldac v out v out d7-d0 clr pd v dd ref in v dd = 3v to 5v v dd agnd dgnd 10 m f 0.1 m f figure 27. typical configuration selecting the internal reference figure 28 shows a typical setup for the AD7801 when using an external reference. the reference range for the AD7801 is from 1 v to v dd /2 v. higher values of reference can be incorporated but will saturate the output at both the top and bottom end of the transfer function. there is a gain of two from input to output on the AD7801. suitable references for 5 v operation are the ad780 and ref192. for 3 v operation a suitable external reference would be the ad589 a 1.23 v bandgap reference. data bus control inputs AD7801 cs wr ldac v out v out d7-d0 clr pd v dd ref in v dd = 3v to 5v v dd agnd dgnd 10 m f 0.1 m f 0.1 m f ext ref v out v in gnd ad780/ref192 with v dd = 5v or ad589 with v dd = 3v figure 28. typical configuration using an external reference microprocessor interfacing AD7801Cadsp-2101/adsp-2103 interface figure 29 shows an interface between the AD7801 and the adsp- 2101/ads p-2103. the fast interface timing associated with the AD7801 allows easy interface to the adsp-2101/adsp -2103. ldac is permanently tied low in this circuit so the dac output is updated on the rising edge of the wr signal. data is loaded to the AD7801 input register using the following adsp-21xx instruction. dm(dac) = mr0 mr0 = adsp-21xx mr0 register. dac = decoded dac address. addr decode en address bus AD7801* cs ldac wr db7 db0 data bus * additional circuitry omitted for clarity. dma14 dma0 dms wr dmd15 dmd0 adsp-2101*/ adsp-2103* figure 29. AD7801Cadsp-2101/adsp-2103 interface AD7801Ctms320c20 interface figure 30 shows an interface between the AD7801 and the tms320c20. d ata is loaded to the AD7801 using the following instruction: out dac, d dac = decoded dac address. d = data memory address. addr decode en address bus AD7801* cs ldac wr db7 db0 data bus * additional circuitry omitted for clarity. a15 a0 is strb d15 d0 tms320c20 r/ w figure 30. AD7801Ctms320c20 interface
AD7801 C11C rev. 0 in the circuit shown the ldac is hardwired low thus the dac output is updated on the rising edge of wr . some applications may require synchronous updating of the dac in the AD7801. in this case the ldac signal can be driven from an external timer or can be controlled by the microprocessor. one option for synchronous updating is to decode the ldac from the ad- dress bus so a write operation at this address will synchronously update the dac output. a simple or gate with one input driven from the decoded address and the second input from the wr signal will implement this function. AD7801C8051/8088 interface figure 31 shows a serial interface between the AD7801 and the 8051/8088 processors. addr decode en address bus AD7801* cs ldac wr db7 db0 data bus * additional circuitry omitted for clarity. a15 a8 psen or den wr ad7 ad0 8051/8088* ale octal latch figure 31. AD7801C8051/8088 interface applications bipolar operation using the AD7801 the AD7801 has been designed for unipolar operation but bipolar operation is possible using the circuit in figure 32. the circuit shown is configured for an output voltage range of C5 v to +5 v. rail-to-rail operation at the amplifier output is achievable by using an ad820 or op295 as the output amplifier. the out put voltage for any input code can be calculated as follows: v o = r 2 1 + r 4 r 3 ? ? ? ? / r 1 + r 2 () 2 v ref d 256 ? ? ? ? - v ref r 4 r 3 ? ? ? ? ? ? where d is the decimal equivalent of the code loaded to the dac and v ref is the reference voltage input. with v ref = 2.5 v, r1 = r3 = 10 k w and r2 = r4 = 20 k w and v dd = 5 v. v o = 10 d 256 ? ? ? ? 5 data bus control inputs AD7801 cs wr ldac v out d7-d0 clr pd v dd ref in v dd = 3v to 5v v dd agnd dgnd 10 m f 0.1 m f 0.1 m f ext ref v out v in gnd ad780/ref192 with v dd = 5v or ad589 with v dd = 3v r1 10k w r2 20k w +5v 5v r3 10k w r4 20k w C5v ad820/ op295 figure 32. bipolar operation using the AD7801 decoding multiple AD7801s in a system the cs pin on the AD7801 can be used in applications to decode a number of dacs. in this application, all dacs in the system receive the same input data, but only the cs to one of the dacs will be active at any one time allowing access to one channel in the system. the 74hc139 is used as a two-to-four line decoder to address any of the dacs in the system. to prevent timing errors from occurring, the enable input on the 74hc139 should be brought to its inactive state while the coded address inputs are changing state. figure 33 shows a diagram of a typical setup for decoding multiple AD7801 devices in a system. the built-in power-on reset circuit on the AD7801 ensures that the outputs of all dacs in the system power up with zero volts on their outputs. AD7801 cs wr d0 d7 ldac v out AD7801 cs wr d0 d7 ldac v out AD7801 cs wr d0 d7 ldac v out AD7801 cs wr d0 d7 ldac v out 74hc139 v cc v dd 1 g 1a 1b dgnd enable coded address wr 1y0 1y1 1y2 1y3 data bus figure 33. decoding multiple AD7801s
AD7801 C12C rev. 0 AD7801 as a digitally programmable indicator a digitally programmable upper limit detector using the dac is shown in figure 34. the upper limit for the test is loaded to the dac, which in turn sets the limit for the cmp04. if a signal at the v in input is not below the programmed value, an led will indicate the fail condition. 1/4 cmp-04 AD7801 v dd refin dgnd agnd d7 d0 v out v in pass/ 1/6 74hc05 1k w pass 1k w fail 10 f 0.1 f +5v dv dd figure 34. digitally programmable indicator programmable current source figure 35 shows the AD7801 used as the control element of a programmable current source. in this circuit the full-scale current is set to 1 ma. the output voltage from the dac is applied across the current setting resistor of 4.7 k w in series with the full-scale setting resistor of 470 w . suitable transistors to place in the feedback loop of the amplifier include the bc107 and the 2n3904, which enable the current source to operate from a minimum v source of 6 v. the operating range is determined by the operating characteristics of the transistor. suitable amplifiers include the ad820 and the op295, both of which have rail-to-rail operation on their outputs. the current for any digital input code can be calculated as follows: i = 2 v ref d () 256 (5 k w ) () AD7801 v out ref in v dd = 5v v dd agnd dgnd 10? 0.1? 0.1? ext ref v out v in gnd ad780/ ref192 with v dd = 5v 4.7k w 470 w +5v ad820/ op295 2n3904/ bc107 v source load figure 35. programmable current source coarse and fine adjustment using two AD7801s the two dacs can be paired together to form a coarse and fine adjustment function for a setpoint as shown in figure 36. in this circuit, the first dac is used to provide the coarse adjustment and the second dac is used to provide the fine adjustment. varying the ratio of r1 and r2 will vary the relative effect of the coarse and fine tune elements in the circuit. for the resistor values shown, the second dac has a resolution of 148 m v giving a fine tune range of 38 mv (approximately 2 lsb) for operation with a v dd of 5 v and a reference of 2.5 v. the amplifier shown allows a rail-to-rail output voltage to be achieved on the output. a typical application for the circuit would be in a setpoint controller. AD7801 v out ref in v dd = 5v v dd agnd dgnd 10? 0.1? 0.1? ext ref v out v in gnd ad780/ ref192 with v dd = 5v or ad589 with v dd = 3v +5v ad820/ op295 r1 390 w AD7801 v out ref in v dd agnd dgnd r2 51.2k w v o r3 51.2k w r4 390 w 0.1? figure 36. coarse and fine adjustment
AD7801 C13C rev. 0 power supply bypassing and grounding in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the AD7801 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. if the AD7801 is in a system where multiple devices require an agnd to dgnd connection, the connection should be made at one point only, a star ground point which should be established as closely as possible to the AD7801. the AD7801 should have ample supply bypassing of 10 m f in parallel with 0.1 m f located as close to the package as possible, ideally right up against the device. the 10 m f capacitors are the tantalum bead type. the 0.1 m f capacitors should have low effective series resistance (esr) and effective series inductance (esi), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switc hing. the power supply lines of the AD7801 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the supply line. fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near reference inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effect of feedthrough through the board. a microstrip technique is by far the best, but not always possible with a double-sided board. in this technique, the component side of the board is dedicated to the ground plane while signal traces are placed on the solder side.
AD7801 C14C rev. 0 20-lead wide body soic (r-20) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45 20 11 10 1 0.5118 (13.00) 0.4961 (12.60) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 20-lead tssop (ru-20) 20 11 10 1 0.260 (6.60) 0.252 (6.40) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 outline dimensions dimensions shown in inches and (mm).
C15C
C16C c2995C12C4/97 printed in u.s.a.

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